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NXP Semiconductors /LPC43xx /C_CAN1 /CLKDIV

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Interpret as CLKDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIVVAL 0RESERVED

Description

CAN clock divider register

Fields

CLKDIVVAL

Clock divider value CAN_CLK = PCLK/(CLKDIVVAL +1)

0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3. 0011: CAN_CLK = PCLK divided by 4. 0100: CAN_CLK = PCLK divided by 5. … 1111: CAN_CLK = PCLK divided by 16.
RESERVED

reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data